RISC-V & Hardware accelerator & CNN

Ability to add custom streaming ALU pipelines (with very wide I/O)

LVE  lightweight vector engine (VHDL, not open source)

  • Adds 10x performance to RISC V, less area than RISC V
  • Ability to add custom streaming ALU pipelines
  • Streams data from small dedicated scratchpad to RISC V ALU

MXP large vector engine (VHDL, not open source)

  • Scalable performance, 10 to 1000x depending on # lanes
  • Each lane has one 32b ALU, about size of RISC V core
  • Adds sub-word SIMD (8b, 16b operations with more parallelism)
  • Ability to add custom streaming ALU pipelines (with very wide I/O)
  • Works with RISC V and other CPUs (eg, ARM)

BNN Accelerator (VHDL not open source)

  • Streaming 3×3 convolutions, 1b weights, 8b input data, 16b activations
  • Currently: LVE version with 2 parallel convolutions

CNN Accelerator (VHDL, not open source)

  • Streaming 3×3 convolutions, 8/12/16b weights, 8/16b data, 16b activations
  • 4-way interleave of input maps to provide greater SIMD parallelism
  • Currently: MXP version with N-2 parallel convolutions, 4-way interleaved
  • Adds 10x performance to RISC V, less area than RISC V
  • Ability to add custom streaming ALU pipelines
  • Streams data from small dedicated scratchpad to RISC V ALU

LBP Accelerator (VHDL, not open source)

  • Streaming 3×3 LBPs for AdaBoost-based machine learning systems